1. Technical Field
This disclosure generally relates to a thin film transistor array and a displaying apparatus using the thin film transistor array.
2. Description of the Related Art
A displaying apparatus using a thin film transistor array (TFT array) has been widely used, and in many case, a pattern of the thin film transistor array is generally formed by a photolithography method.
The photolithography method includes the following processes.
A. A resist applying process in which a photoresist layer is applied onto a substrate having a thin film layer.
B. A pre-baking process in which a solvent on the substrate is removed by baking.
C. An exposing process in which ultraviolet rays are irradiated onto the substrate via a hard mask formed by a laser beam or an electron beam based on pattern data.
D. A developing process in which the resist on an exposed section is removed by using an alkali solution.
E. A post-baking process in which the resist at the unexposed section (pattern part) is hardened by baking.
F. An etching process in which a part of the thin film layer where the resist has not been covered is removed by soaking into an etching liquid or exposing in an etching gas.
G. A resist removing process in which the resist is removed by using an alkali solution or oxygen radical.
When the photolithography method is used, a micro pattern of tens of nm can be formed; however, cost is high due to high-priced equipment and long processes.
In order to reduce the cost, a pattern has been formed by using a printing method such as an inkjet printing method, an aerosol printing method, and an offset printing method, and a thin film transistor array has been formed (refer to Patent Document 1).
First, a conventional thin film transistor array is described. The conventional thin film transistor array has a structure shown in FIG. 15 regardless of using a photolithography method or a printing method for forming a pattern. FIG. 15 is a structural diagram of a conventional thin film transistor array 10. FIG. 15(a) shows a plan view and FIG. 15(b) shows a cross-sectional view along line I-I of FIG. 15 (a). As shown in FIG. 15, the thin film transistor array 10 provides an insulation substrate 11, gate electrodes 12, a gate insulation film 14, source electrodes 15, drain electrodes 16, semiconductor layers 17, and channel regions 17a. In addition, the gate electrode 12 provides a branching section 12a. In FIG. 15, the lengthwise (long length) direction of the source electrode 15 is in the X direction, and the lengthwise direction of the gate electrode 12 is in the Y direction.
The plural gate electrodes 12 are formed by having an approximately constant interval among them on the insulation substrate 11. In order to form the channel regions 17a (described below in detail), each of the plural gate electrodes 12 provides the branching section 12a which branches in an approximately perpendicular direction relative to the direction of the gate electrode 12. For example, in a displaying apparatus, the plural gate electrodes 12 protrude from the thin film transistor array 10 in one direction, are connected to a gate driver IC (not shown) for a scanning signal, and a selection signal is sequentially supplied to the gate electrodes 12.
The gate insulation film 14 is formed on the gate electrodes 12. The plural source electrodes 15 are formed on the gate insulation film 14 by having an approximately constant interval among them so that the plural source electrodes 15 cross the plural gate electrodes 12 in the planar view.
For example, in a displaying apparatus, the plural source electrodes 15 protrude from the thin film transistor array 10 in one direction, are connected to a source driver IC (not shown) for a data signal, and the data signal is supplied to the source electrodes 15.
The plural drain electrodes 16 are formed in regions surrounded by the corresponding plural gate electrodes 12 and the corresponding source electrodes 15 in the planar view on the same layer on which the source electrodes 15 are formed. The semiconductor layer 17 is formed on the source electrode 15 and the drain electrode 16.
The channel region 17a is formed in the semiconductor layer 17 at a position where the source electrode 15 faces the drain electrode 16. When a voltage is applied to the gate electrode 12, electrons (or holes) in the semiconductor layer 17 connected to the source electrode 15 and the drain electrode 16 are extracted to a position directly below the branching section 12a of the gate electrode 12, and the source electrode 15 is electrically connected to the drain electrode 16. That is, an electron (hole) flowing region is called a channel region.
In addition, in the channel region 17a, a length of the channel region 17a at a position where the source electrode 15 faces the drain electrode 16 is called a channel width (the X direction in FIG. 15), and an interval between the source electrode 15 and the drain electrode 16 is called a channel length (the Y direction in FIG. 15). The branching section 12a of the gate electrode 12 must be under the channel region 17a so that an electric field is applied to the channel region 17a. 
The gate insulation film 14 insulates the gate electrode 12 from the source electrode 15 and the drain electrode 16, and turns on/off the thin film transistor array 10 by applying an electric field applied to the gate electrode 12 to the channel region 17a formed between the source electrode 15 and the drain electrode 16.
In the conventional thin film transistor array 10, in order to form the channel region 17a, the branching section 12a which branches in an approximately perpendicular direction relative to the direction of the gate electrode 12 is formed regardless of using a photolithography method or a printing method for forming a pattern.
[Patent Document 1] Japanese Translation of PCT International Application No. 2006-516754
However, as shown in FIG. 15, the gate insulation film 14 is formed between the gate electrode 12 and the source electrode 15 (the drain electrode 16); therefore, the gate electrode 12 and the source electrode 15 (the drain electrode 16) are separately formed.
In addition, as described above, the branching section 12a of the gate electrode 12 must be under the channel region 17a so that an electric field is applied to the channel region 17a formed between the source electrode 15 and the drain electrode 16.
In order to satisfy a positional relationship between the branching section 12a of the gate electrode 12 and the channel region 17a formed between the source electrode 15 and the drain electrode 16, so-called alignment must be performed.
If the alignment is shifted in the X or Y direction of FIG. 15, the positional relationship between the branching section 12a of the gate electrode 12 and the channel region 17a formed between the source electrode 15 and the drain electrode 16 is changed. Consequently, characteristics of the thin film transistor array 10 are changed.